The invention relates generally to bipolar transistor structures, and methods for fabrication thereof. More particularly, the invention relates to bipolar transistor structures that provide bipolar transistor devices with enhanced performance, and methods for fabrication thereof.
Semiconductor structures include semiconductor substrates within and upon which are formed semiconductor devices such as but not limited to resistors, transistors, diodes and capacitors. The semiconductor devices are connected and interconnected using patterned conductor layers that are separated by dielectric layers.
In addition to conventional field effect transistor structures that are used within the context of semiconductor circuits, semiconductor circuits may also commonly include alternative transistor structures, such as but not limited to bipolar transistor structures. Bipolar transistors are often desirable within the context of semiconductor circuits insofar as bipolar transistors often operate at elevated switching speeds in comparison with field effect transistors.
Bipolar transistors in general differ in comparison with field effect transistors insofar as bipolar transistors operate within the context of charge carrier transfer through semiconductor junctions, while field effect transistors operate within the context of charge carrier transfer incident to an electric field gradient imposed within a semiconductor substrate by a gate that is isolated from the semiconductor substrate by a gate dielectric. Thus, while field effect transistor performance is often influenced by a gate-to-gate dielectric interface or a gate dielectric-to-semiconductor channel interface characteristics, bipolar transistor performance is often influenced by an emitter-to-base junction interface or base-to-collector junction interface characteristics.
Thus desirable are bipolar transistor structures and devices, and methods for fabricating bipolar transistor structures and devices, that provide bipolar transistors having enhanced performance due to optimized junction interface characteristics.